During a detection process of an array substrate, alignment settings are required, wherein the alignment process includes: applying a common voltage signal on a pad and using a detection device to emit electronic beams to an alignment mark region of the array substrate, such that a metal region in the alignment mark region will absorb electrons emitted by the detection device to form an electric current, whereas an etched region will not absorb electrons because there is no metal. The detection device determines whether the alignment is correct by sensing the electric current.
FIG. 1 shows a conventional array substrate including a region where an alignment mark structure is formed. The array substrate comprises a glass substrate 1, a common electrode 2, a gate insulation layer 3, an etch barrier layer 4, a passivation layer 5, and a pixel electrode layer 6. An alignment mark is fabricated on the pixel electrode layer 6, and the pixel electrode layer 6 is connected with the common electrode 2 via holes formed in the etch barrier layer 4, the gate insulation layer 3, and the passivation layer 5. In order to avoid a break in the pixel electrode layer 6 deposited in the aforementioned via hole region (as shown in the circled portion of FIG. 1), the gradients of the sidewalls of the via holes and the sizes of the via holes need to be strictly consistent. However, it is difficult to control the gradients of the sidewall of the via holes in the actual process of etching the via holes. Therefore, failure of the alignment mark often occurs.